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This guide provides expert principles for designing and auditing system-level experiments in computer architecture (e.g., for ASPLOS-level conferences). It details the proper usage of various instruments—from real silicon and FPGAs to cycle-level simulators and analytical models—ensuring that every claim is matched to a valid, stated error model. It emphasizes workload selection, establishing strong baselines, performing rigorous ablation studies, and honestly reporting measurement noise and limitations to maintain scientific credibility.

A comprehensive guide for establishing research reproducibility in Electronic Design Automation (EDA). It details best practices for pinning benchmark suites, disclosing specific tool versions (open/commercial), documenting technology nodes (PDKs), and handling stochastic data flows (seeds, variance). Essential for ensuring that semiconductor design claims and ML-for-EDA results are credible and verifiable by the academic community.

This guide outlines the rigorous methodology for ensuring that computational research results, especially those involving hardware architecture and simulation, are fully reproducible. It emphasizes pinning the entire result chain—from simulator commits and configuration files to workloads, sampling recipes, and statistics scripts—and mandates creating a manifest for every figure. Key practices include recording machine state for silicon runs and containerizing the environment to prevent data drift.

This guide provides a rigorous framework for evaluating computer architecture designs. It covers critical steps including selecting the appropriate simulation instrument (from analytical models to silicon measurements), constructing robust baselines, performing ablation studies, and reporting comprehensive metrics like geomeans and full overhead accounting to ensure scientific validity.