Skill UI

This skill automates the Design Space Exploration (DSE) process, crucial for computer architecture and Electronic Design Automation (EDA). It runs complex simulations, analyzes performance metrics, and systematically tunes parameters (e.g., cache size, pipeline width) across a defined parameter space. It iterates until the objective metric is optimized or a defined timeout is reached, making it ideal for complex hardware tuning and system design.

This skill guides organizations in implementing and managing security controls required by PCI DSS 4.0.1. It covers the 12 requirements across 6 control objectives for protecting cardholder data that is stored, processed, or transmitted. Use this when scoping a Cardholder Data Environment (CDE), enhancing security architecture, or preparing for mandatory PCI compliance assessments, including customized validation and MFA implementation.

A detailed model of the ACM/IEEE Design Automation Conference (DAC) research manuscript review process. This guide explains the double-blind, TPC-driven, and single-shot nature of the evaluation, emphasizing the critical balance between genuine novelty and measured Quality-of-Results (QoR). It outlines the high standards for evidence fairness, benchmark credibility, and ablation studies required for acceptance, differentiating DAC's approach from architecture and software venues.

A comprehensive guide on achieving scientific reproducibility for complex computer architecture and system simulations. It details how to manage and pin all dependencies—including simulator commit hashes, local patches, workload binaries, hardware states, and post-processing scripts—to ensure that every reported figure and number can be accurately regenerated, regardless of time or environment changes.

This guide details the process of preparing complex research artifacts (simulators, configurations, traces, and scripts) for post-acceptance evaluation, especially for microarchitecture papers. It outlines best practices for achieving ACM badges like 'Available' and 'Reproducible,' focusing on structuring the code base with tiered entry points (smoke, key, full) and handling dependencies, licensed data, and simulation time constraints.

A comprehensive model detailing the entire academic review pipeline for microarchitecture papers, anchored to major conferences like MICRO. It outlines the timeline, from initial submission and double-blind review through the rebuttal/revision window, to final notification. The guide details what expert reviewers focus on—including mechanism novelty, methodology credibility, and cost honesty—providing authors with actionable strategies for strengthening their work through the academic publication lifecycle.