Skill UI

This comprehensive guide provides a detailed audit checklist for submitting research manuscripts to major design automation conferences (e.g., DAC). It covers critical steps such as the two-stage abstract/manuscript timeline, adherence to the strict 6+1 page format, ensuring double-blind anonymization (removing all identifying metadata), declaring TPC conflicts, and mitigating common submission risks. Essential reading for researchers preparing for high-stakes academic submissions.

This comprehensive guide assists researchers and practitioners in selecting the optimal venue and track (e.g., DAC, ICCAD, ISCA) for their electronic design automation (EDA) or chip-design project. It clarifies the critical distinction between the archival Research Manuscript track and the industry-facing Engineering Track at DAC, emphasizing the need to frame contributions using measurable Quality of Results (QoR) improvements, novel algorithms, or real-world industrial lessons.

A comprehensive guide modeling the USENIX FAST conference submission review pipeline. It details the double-blind review process, the author-response period, and clarifies the four distinct outcomes (Accept, Shepherding, One-shot Revision, Reject). This resource helps authors understand the strategic implications of the review stages, especially how a one-shot revision differs from standard journal revisions, providing actionable advice for maximizing submission chances.

A comprehensive style guide for structuring and refining robotics research manuscripts for top-tier conferences like ICRA. It dictates moving from technique-speak to task-first narratives, emphasizing figure-first presentation, rigorous quantification of claims, and adhering to strict page budgets to maximize reviewer impact and clarity.

This guide provides rigorous guidelines for structuring and validating experimental results in computer architecture papers. It covers essential aspects like declaring simulation methodology contracts, ensuring result reproducibility through manifest files, selecting representative workloads, and performing detailed attribution and sensitivity analyses to distinguish true architectural gains from modeling artifacts.

This guide provides authors with best practices for improving the reproducibility and verifiable availability of communication experiments for submission to JOC. It clarifies the journal's current status regarding artifact badges, offering actionable advice on openly sharing code, data, and simulation parameters to enhance credibility while maintaining academic rigor.

This guide helps researchers determine the correct academic venue for their work in parallel and concurrent computing. It clarifies the scope of PPoPP versus related conferences (CGO, PLDI, ASPLOS, HPCA, POPL, etc.) by asking: 'Is the parallelism the point, or is it the setting?' Use this framework to distinguish contributions focused on parallel algorithms, compiler optimization, concurrency theory, or hardware microarchitecture.

This comprehensive guide outlines the strict criteria for submitting a paper to the SenSys conference after the 2026 merger. It clarifies that the core contribution must be a built, measured sensing or embedded system, demonstrating value based on physical resources like energy, memory, and latency on real hardware, rather than being a pure algorithm or networking mechanism.