Skill UI

A comprehensive guide modeling the USENIX FAST conference submission review pipeline. It details the double-blind review process, the author-response period, and clarifies the four distinct outcomes (Accept, Shepherding, One-shot Revision, Reject). This resource helps authors understand the strategic implications of the review stages, especially how a one-shot revision differs from standard journal revisions, providing actionable advice for maximizing submission chances.

This guide provides a comprehensive project management workflow for submitting research to the USENIX FAST conference. It covers the entire academic lifecycle, detailing milestones from initial topic selection and evidence locking to double-blind submission, author response, and managing the complex two-deadline cycle, including potential one-shot revisions. Use this to back-plan your research schedule based on concrete storage measurement timelines.

A comprehensive guide for researchers preparing academic artifacts for voluntary, post-acceptance evaluation (e.g., HPCA). It outlines best practices for structuring submissions for cold-start evaluators, defining reproducibility tiers (full reproduction, regeneration from logs, inspection), and managing computational budgets to successfully earn IEEE reproducibility badges.

A comprehensive guide for auditing and improving the scientific rigor of hardware architectural evaluations (e.g., HPCA style). It emphasizes establishing a clear 'fidelity contract' defining tools, scope, and configurations. It requires that all performance claims are backed by credible instruments, mandates capturing full machine state provenance, ensuring honest baseline tuning, and reporting results via per-workload distributions rather than single means.

A detailed guide on positioning a computer architecture paper within the broader academic literature. It teaches authors to write a 'lineage with structural deltas,' moving beyond mere citation lists. The guidelines cover sweeping multiple databases (like dblp and IEEE Xplore), identifying concrete structural improvements (deltas), and adhering to strict academic rules, such as citing all authors and maintaining un-blinded bibliography integrity.

This guide outlines the rigorous methodology for ensuring that computational research results, especially those involving hardware architecture and simulation, are fully reproducible. It emphasizes pinning the entire result chain—from simulator commits and configuration files to workloads, sampling recipes, and statistics scripts—and mandates creating a manifest for every figure. Key practices include recording machine state for silicon runs and containerizing the environment to prevent data drift.

A comprehensive audit checklist for submitting a paper to the HPCA conference. This guide covers critical checkpoints including the two-step abstract-and-conflict registration, adherence to the IEEE template (11-page limit), maintaining double-blind anonymity, ensuring full author listing in references, and disclosing AI-generated content. Use this to mitigate desk-reject risks and ensure timely submission readiness.

This guide provides rigorous structural and stylistic guidelines for writing top-tier academic papers in computer architecture (specifically for HPCA). It emphasizes building arguments around a single, measurable mechanism-to-behavior claim, quantifying the motivation with measured costs, ensuring all proposed mechanisms are checkable, and making sure every performance number is anchored to a specific instrument or simulation environment. It details the essential 'first-page arc' structure.

This guide provides a specialized framework for authors targeting the IACR Conference on Cryptographic Hardware and Embedded Systems (CHES). It details the specific scope, evidence bar, and framing techniques required for cryptographic hardware papers, ensuring submissions meet the high standards of the community. It helps reposition work from journal or general CS styles.

A comprehensive guide for designing and auditing empirical experiments in signal processing, audio, and speech domains. It emphasizes matching standard metrics (e.g., WER, SI-SDR, PSNR) to specific tasks, establishing current strong baselines, and systematically sweeping operating conditions (like SNR or reverberation time) to ensure robust, reliable, and publication-ready results.

A comprehensive guide for authors submitting to major signal processing conferences like ICASSP. It details how to audit, define, and precisely position a paper's novelty by comparing it against specific literature lanes (SPS journals, conferences, and ML venues). Learn to articulate the technical delta against the nearest work in a constrained, four-page format.

This comprehensive guide outlines the full project management lifecycle for submitting research papers to the ICASSP conference (IEEE Signal Processing Society). It details the annual timeline, critical milestones, backward planning heuristics, and best practices across various submission tracks to ensure timely and successful publication.