Skill UI

A comprehensive guide for computer science authors targeting high-performance parallel and distributed computing venues like HPDC. It assists in conference fit evaluation, manuscript re-framing (from journal/arXiv to conference narrative), identifying evidence gaps, and structuring contributions for optimal review success in cloud/HPC systems and distributed settings. Ideal for determining submission strategy.

A comprehensive guide for researchers preparing academic artifacts for voluntary, post-acceptance evaluation (e.g., HPCA). It outlines best practices for structuring submissions for cold-start evaluators, defining reproducibility tiers (full reproduction, regeneration from logs, inspection), and managing computational budgets to successfully earn IEEE reproducibility badges.

A comprehensive guide for auditing and improving the scientific rigor of hardware architectural evaluations (e.g., HPCA style). It emphasizes establishing a clear 'fidelity contract' defining tools, scope, and configurations. It requires that all performance claims are backed by credible instruments, mandates capturing full machine state provenance, ensuring honest baseline tuning, and reporting results via per-workload distributions rather than single means.

A detailed guide on positioning a computer architecture paper within the broader academic literature. It teaches authors to write a 'lineage with structural deltas,' moving beyond mere citation lists. The guidelines cover sweeping multiple databases (like dblp and IEEE Xplore), identifying concrete structural improvements (deltas), and adhering to strict academic rules, such as citing all authors and maintaining un-blinded bibliography integrity.

This guide outlines the rigorous methodology for ensuring that computational research results, especially those involving hardware architecture and simulation, are fully reproducible. It emphasizes pinning the entire result chain—from simulator commits and configuration files to workloads, sampling recipes, and statistics scripts—and mandates creating a manifest for every figure. Key practices include recording machine state for silicon runs and containerizing the environment to prevent data drift.

A comprehensive audit checklist for submitting a paper to the HPCA conference. This guide covers critical checkpoints including the two-step abstract-and-conflict registration, adherence to the IEEE template (11-page limit), maintaining double-blind anonymity, ensuring full author listing in references, and disclosing AI-generated content. Use this to mitigate desk-reject risks and ensure timely submission readiness.

This guide provides rigorous structural and stylistic guidelines for writing top-tier academic papers in computer architecture (specifically for HPCA). It emphasizes building arguments around a single, measurable mechanism-to-behavior claim, quantifying the motivation with measured costs, ensuring all proposed mechanisms are checkable, and making sure every performance number is anchored to a specific instrument or simulation environment. It details the essential 'first-page arc' structure.

A comprehensive guide for positioning computer architecture manuscripts for the IEEE HPCA conference. It covers ideal scope (accelerators, memory systems, interconnects), required evidence (benchmarks, performance/energy tradeoffs), and strategic framing needed to appeal to top-tier hardware reviewers. Use it to refine your narrative and ensure your contribution meets the high standards of high-performance computing research.

This skill helps authors determine if their manuscript is suitable for the International Conference for High Performance Computing, Networking, Storage and Analysis (SC). It provides comprehensive guidelines on framing the work, establishing the evidence bar (requiring scale, performance portability, and systems impact), and positioning the contribution for a top-tier HPC flagship venue. Use it for strategic venue selection and manuscript re-framing.

A comprehensive guide for authors submitting computer architecture papers to ISCA. It details the scope fit, required evidence (simulation or hardware), effective framing strategies, and provides comparisons with similar top-tier venues (like MICRO, HPCA). It helps authors refine their manuscript to meet the rigorous standards of a flagship conference.

This guide maps out the complex, multi-year pipeline for submitting research papers to top-tier computer architecture conferences (e.g., MICRO, ISCA, ASPLOS, HPCA). It details the entire lifecycle, from initial abstract submission and revision through simulation, implementation, and final symposium presentation. It critically emphasizes that the evaluation schedule—the compute-bound sweep queues and simulation cycles—is the most critical path and primary bottleneck for academic research.

This comprehensive guide outlines the rigorous methodology required for designing high-impact evaluations of parallel systems and algorithms for top-tier conferences. It stresses that contributions must demonstrate the 'twin bar': both concurrency correctness (e.g., linearizability) and measurable scalability (e.g., strong vs. weak scaling). It covers best practices for establishing strong baselines, managing measurement hygiene (variance, pinning), and anticipating advanced reviewer scrutiny in HPC.