Skill UI

Generates a comprehensive, structured, and blameless incident postmortem document. This skill is designed for Root Cause Analysis (RCA), P1/P2 incident reviews, and outage reports, ensuring the focus remains on systemic gaps and preventative action items rather than individual blame. It guides the user through gathering all necessary details, from the timeline and impact to defining concrete action owners and due dates.

CHIPSEC is an open-source framework designed to assess the low-level security configuration of x86 platform firmware and hardware. It verifies critical security controls such as SPI flash write protection, BIOS locks, SMM/SMRR configuration, and Secure Boot variable integrity. Users can run automated tests, dump SPI flash memories for forensics, and detect potential firmware implants that persist below the operating system layer.

KubeEye is a comprehensive cluster inspection tool designed for Kubernetes environments, particularly within KubeSphere. It systematically detects issues across workloads, nodes, and configurations by integrating multiple policy engines, including OPA/Rego, PromQL, file integrity checks, kernel parameter validation, and systemd health checks. Users can define custom inspection rules (InspectRule), schedule checks (InspectPlan), and retrieve detailed reports (InspectResult) to ensure cluster compliance and stability.

A sophisticated and print-friendly presentation template designed for explaining complex system architectures and data pipelines. Featuring a blueprint grid, cream background, and rust red accents, this deck is ideal for technical deep dives in engineering and system design.

A structured workflow designed to prevent 'reinventing the wheel.' Before writing custom code, this skill guides the user through analyzing needs, conducting parallel searches across multiple channels (npm, PyPI, GitHub, MCP), evaluating candidate solutions based on maintainability and community support, and making a decision (Adopt, Extend, or Custom Build). It ensures that solutions leverage existing, proven libraries and patterns.

This guide provides expert principles for designing and auditing system-level experiments in computer architecture (e.g., for ASPLOS-level conferences). It details the proper usage of various instruments—from real silicon and FPGAs to cycle-level simulators and analytical models—ensuring that every claim is matched to a valid, stated error model. It emphasizes workload selection, establishing strong baselines, performing rigorous ablation studies, and honestly reporting measurement noise and limitations to maintain scientific credibility.

This guide outlines the rigorous standards for evaluating systems research, particularly for top-tier conferences like ATC. It provides detailed instructions on designing reproducible experiments, establishing fair baselines, utilizing realistic workloads, and reporting critical metrics such as tail latency, variance, and resource cost, ensuring the highest level of scientific rigor.

This guide provides comprehensive standards for designing, auditing, and reporting empirical evaluations in database systems research. It emphasizes the principle that evidence must proportionally match the claim, requiring the use of real-world workloads, fair and tuned baselines, thorough measurement of variance and state (warm/cold), and fully reproducible evaluation harnesses. It also outlines the higher bar for 'Experiments & Analysis' papers.

A comprehensive guide for designing and auditing empirical experiments in signal processing, audio, and speech domains. It emphasizes matching standard metrics (e.g., WER, SI-SDR, PSNR) to specific tasks, establishing current strong baselines, and systematically sweeping operating conditions (like SNR or reverberation time) to ensure robust, reliable, and publication-ready results.

This guide provides comprehensive standards for designing, executing, and reporting systems experiments for top-tier academic venues (like ICDE). It emphasizes methodological rigor, including mandatory ablation studies, reporting variance and tail latency (p99), demonstrating scaling trends (curves over points), disclosing cost trade-offs, and ensuring full hardware and software reproducibility to withstand adversarial review.

A comprehensive guide for authors targeting the IEEE CASE conference. This tool helps assess manuscript fit by focusing on automation science, manufacturing, logistics, and cyber-physical systems. It guides authors on how to re-frame algorithmic designs with practical operational evidence, structure the contribution, and anticipate reviewer expectations for top-tier automation venues.

A comprehensive guide for designing and auditing rigorous experiments for sensing systems and information processing claims. It emphasizes the necessity of measuring performance on real hardware (not simulation), accurately instrumenting ground truth, quantifying energy consumption, latency, and physical footprint, and establishing fair, skeptical baselines. This ensures scientific rigor and reproducibility in research submissions.