Skill UI

A comprehensive technical module covering foundational deep learning principles and cutting-edge computer vision architectures, drawing from Yann LeCun's research. Topics include CNN fundamentals, backpropagation theory, and advanced self-supervised learning (SSL) models such as SimCLR, MAE, and the modern Joint Embedding Predictive Architecture (JEPA). Provides detailed theoretical explanations and complete PyTorch code for implementation.

This skill automates the Design Space Exploration (DSE) process, crucial for computer architecture and Electronic Design Automation (EDA). It runs complex simulations, analyzes performance metrics, and systematically tunes parameters (e.g., cache size, pipeline width) across a defined parameter space. It iterates until the objective metric is optimized or a defined timeout is reached, making it ideal for complex hardware tuning and system design.

A comprehensive guide for authors targeting ASPLOS, a premier conference at the intersection of programming languages, operating systems, and computer architecture. This tool assists in positioning cross-layer evidence, framing the contribution, and ensuring the manuscript meets the strict technical and academic standards required for top-tier systems research.

This guide provides expert principles for designing and auditing system-level experiments in computer architecture (e.g., for ASPLOS-level conferences). It details the proper usage of various instruments—from real silicon and FPGAs to cycle-level simulators and analytical models—ensuring that every claim is matched to a valid, stated error model. It emphasizes workload selection, establishing strong baselines, performing rigorous ablation studies, and honestly reporting measurement noise and limitations to maintain scientific credibility.

A detailed guide on positioning a computer architecture paper within the broader academic literature. It teaches authors to write a 'lineage with structural deltas,' moving beyond mere citation lists. The guidelines cover sweeping multiple databases (like dblp and IEEE Xplore), identifying concrete structural improvements (deltas), and adhering to strict academic rules, such as citing all authors and maintaining un-blinded bibliography integrity.

This guide provides rigorous structural and stylistic guidelines for writing top-tier academic papers in computer architecture (specifically for HPCA). It emphasizes building arguments around a single, measurable mechanism-to-behavior claim, quantifying the motivation with measured costs, ensuring all proposed mechanisms are checkable, and making sure every performance number is anchored to a specific instrument or simulation environment. It details the essential 'first-page arc' structure.

A comprehensive guide for positioning computer architecture manuscripts for the IEEE HPCA conference. It covers ideal scope (accelerators, memory systems, interconnects), required evidence (benchmarks, performance/energy tradeoffs), and strategic framing needed to appeal to top-tier hardware reviewers. Use it to refine your narrative and ensure your contribution meets the high standards of high-performance computing research.

A comprehensive guide for authors submitting computer architecture papers to ISCA. It details the scope fit, required evidence (simulation or hardware), effective framing strategies, and provides comparisons with similar top-tier venues (like MICRO, HPCA). It helps authors refine their manuscript to meet the rigorous standards of a flagship conference.

This guide provides rigorous guidelines for structuring and validating experimental results in computer architecture papers. It covers essential aspects like declaring simulation methodology contracts, ensuring result reproducibility through manifest files, selecting representative workloads, and performing detailed attribution and sensitivity analyses to distinguish true architectural gains from modeling artifacts.

A comprehensive guide on achieving scientific reproducibility for complex computer architecture and system simulations. It details how to manage and pin all dependencies—including simulator commit hashes, local patches, workload binaries, hardware states, and post-processing scripts—to ensure that every reported figure and number can be accurately regenerated, regardless of time or environment changes.

This guide provides expert advice on positioning research papers for top-tier computer architecture conferences (e.g., ISCA, MICRO, ASPLOS). It teaches authors how to identify the 'center-of-gravity' of their novelty—whether it lies in the hardware organization, the hardware/software contract, or the software layer alone—to maximize review acceptance chances and successfully navigate the competitive academic publication landscape.

A comprehensive guide detailing the specific conventions required for submitting high-quality, data-driven papers in computer architecture to top-tier conferences like ISCA. It covers structuring the core argument around a single insight, developing measured motivation sections, describing mechanisms with checkable precision, and calibrating quantitative claims with empirical data and instruments. Essential for academic research communication in hardware design.