Skill UI

This guide outlines the rigorous methodology for ensuring that computational research results, especially those involving hardware architecture and simulation, are fully reproducible. It emphasizes pinning the entire result chain—from simulator commits and configuration files to workloads, sampling recipes, and statistics scripts—and mandates creating a manifest for every figure. Key practices include recording machine state for silicon runs and containerizing the environment to prevent data drift.

This guide details the academic review process for HPCA, including the double-blind review format, the structure of the single combined rebuttal/revision window, and the dynamics of program-committee meetings. Use this to set clear expectations, predict outcomes, and strategically prepare your rebuttal to maximize your paper's chances of acceptance.

A comprehensive audit checklist for submitting a paper to the HPCA conference. This guide covers critical checkpoints including the two-step abstract-and-conflict registration, adherence to the IEEE template (11-page limit), maintaining double-blind anonymity, ensuring full author listing in references, and disclosing AI-generated content. Use this to mitigate desk-reject risks and ensure timely submission readiness.

This guide details the necessary workflow for organizing supplementary academic content, such as code, extensive methodologies, and raw data, across various conference submission phases. It emphasizes placing only core arguments in the main body, keeping sensitive materials anonymized in the mirror, and preparing a staging shelf for efficient revision.

This guide helps researchers determine the most appropriate conference venue (e.g., HPCA, ISCA, MICRO, ASPLOS) for their microarchitecture or systems research paper. It outlines key criteria, such as whether the contribution is a measured microarchitectural cost, a buildable mechanism, or a measurable characterization, and how to strategically route the project based on its novelty and evidence.

This detailed project management skill provides a comprehensive, backward-planning guide for submitting to highly structured academic conferences, such as HPCA. It maps out critical milestones—from initial venue fit and evidence locking to review, revision, and final camera-ready submission—while identifying common failure modes and coordination requirements to maximize acceptance chances.

This guide provides rigorous structural and stylistic guidelines for writing top-tier academic papers in computer architecture (specifically for HPCA). It emphasizes building arguments around a single, measurable mechanism-to-behavior claim, quantifying the motivation with measured costs, ensuring all proposed mechanisms are checkable, and making sure every performance number is anchored to a specific instrument or simulation environment. It details the essential 'first-page arc' structure.

A comprehensive guide for positioning computer architecture manuscripts for the IEEE HPCA conference. It covers ideal scope (accelerators, memory systems, interconnects), required evidence (benchmarks, performance/energy tradeoffs), and strategic framing needed to appeal to top-tier hardware reviewers. Use it to refine your narrative and ensure your contribution meets the high standards of high-performance computing research.

This skill helps authors determine if their manuscript is suitable for the International Conference for High Performance Computing, Networking, Storage and Analysis (SC). It provides comprehensive guidelines on framing the work, establishing the evidence bar (requiring scale, performance portability, and systems impact), and positioning the contribution for a top-tier HPC flagship venue. Use it for strategic venue selection and manuscript re-framing.

A comprehensive guide for authors submitting computer architecture papers to ISCA. It details the scope fit, required evidence (simulation or hardware), effective framing strategies, and provides comparisons with similar top-tier venues (like MICRO, HPCA). It helps authors refine their manuscript to meet the rigorous standards of a flagship conference.

This guide maps out the complex, multi-year pipeline for submitting research papers to top-tier computer architecture conferences (e.g., MICRO, ISCA, ASPLOS, HPCA). It details the entire lifecycle, from initial abstract submission and revision through simulation, implementation, and final symposium presentation. It critically emphasizes that the evaluation schedule—the compute-bound sweep queues and simulation cycles—is the most critical path and primary bottleneck for academic research.

This comprehensive guide outlines the rigorous methodology required for designing high-impact evaluations of parallel systems and algorithms for top-tier conferences. It stresses that contributions must demonstrate the 'twin bar': both concurrency correctness (e.g., linearizability) and measurable scalability (e.g., strong vs. weak scaling). It covers best practices for establishing strong baselines, managing measurement hygiene (variance, pinning), and anticipating advanced reviewer scrutiny in HPC.