Skill UI

This skill automates the Design Space Exploration (DSE) process, crucial for computer architecture and Electronic Design Automation (EDA). It runs complex simulations, analyzes performance metrics, and systematically tunes parameters (e.g., cache size, pipeline width) across a defined parameter space. It iterates until the objective metric is optimized or a defined timeout is reached, making it ideal for complex hardware tuning and system design.

This skill is designed for running comprehensive evaluations of Hugging Face Hub models on local hardware. It supports multiple evaluation frameworks, including `inspect-ai` and `lighteval`, and provides flexibility in backend selection (e.g., `vllm`, Transformers, or `accelerate`) to optimize for performance and compatibility. Use this for local GPU benchmarking, smoke testing, and backend selection, but note that it does not handle remote job orchestration or result publishing.

This skill provides advanced architectural guidelines for generating premium, award-level web experiences. It guides code generation beyond basic HTML/CSS, focusing on creating immersive digital environments. Key areas include sophisticated motion design (scroll-driven narratives, micro-interactions), establishing strong visual identities (e.g., Brutalism, Glassmorphism), and enforcing strict performance best practices like hardware acceleration and accessibility compliance.

CHIPSEC is an open-source framework designed to assess the low-level security configuration of x86 platform firmware and hardware. It verifies critical security controls such as SPI flash write protection, BIOS locks, SMM/SMRR configuration, and Secure Boot variable integrity. Users can run automated tests, dump SPI flash memories for forensics, and detect potential firmware implants that persist below the operating system layer.

This tool is designed to register a Cognitum Seed IoT device, establishing a secure agent bridge and fetching the device's identity. It resolves the specified or default endpoint for connectivity and handles initial trust level assignment. It is crucial for the initial setup, pairing, and status checking of IoT hardware deployments.

A comprehensive guide for researchers in electronics and signal processing preparing submissions to Acta Electronica Sinica (AES). It outlines best practices for proactively structuring, documenting, and disclosing research artifacts—including code, datasets, and hardware designs—to maximize the paper's credibility and chances of acceptance, even without mandatory journal badges. Covers anonymization, reproducibility standards, and proper disclosure in the manuscript.

A comprehensive methodology for designing scientific and reproducible storage evaluations, particularly for high-stakes submissions. This guide covers controlling device state (aging, preconditioning, TRIM), selecting credible workloads (fio, YCSB), matching metrics (P99.9 latency, bytes-written) to claims, and rigorously testing durability and crash consistency on real hardware.

This guide provides comprehensive standards for designing, executing, and reporting systems experiments for top-tier academic venues (like ICDE). It emphasizes methodological rigor, including mandatory ablation studies, reporting variance and tail latency (p99), demonstrating scaling trends (curves over points), disclosing cost trade-offs, and ensuring full hardware and software reproducibility to withstand adversarial review.

Provides comprehensive guidelines for packaging and documenting complex robotics research artifacts (code, simulations, hardware designs, datasets, etc.) for scholarly review. It outlines best practices for ensuring reproducibility, adopting the "five-minute-skeptic standard," and managing the full lifecycle of artifacts from review submission to public acceptance.

A comprehensive guide to designing rigorous, reproducible, and fair experimental protocols for computational science research, particularly for top-tier academic journals. It covers critical elements such as selecting standard benchmark instances, establishing strong baselines, ensuring fair parameter tuning, reporting hardware constraints, and performing robust statistical validation, helping researchers avoid common pitfalls and maximize the scientific validity of their claims.

A comprehensive guide for designing and auditing rigorous experiments for sensing systems and information processing claims. It emphasizes the necessity of measuring performance on real hardware (not simulation), accurately instrumenting ground truth, quantifying energy consumption, latency, and physical footprint, and establishing fair, skeptical baselines. This ensures scientific rigor and reproducibility in research submissions.

This guide helps researchers determine the primary focus of their work—whether it lies in Information Processing (algorithms, estimation) or Sensor Platforms, Tools, and Design Methods (hardware, deployment). It provides a structured methodology for selecting the most appropriate academic venue (e.g., SenSys, MobiSys, INFOCOM) based on the project's technical contribution and maturity.