Skill UI

This guide helps researchers determine the most appropriate conference venue (e.g., HPCA, ISCA, MICRO, ASPLOS) for their microarchitecture or systems research paper. It outlines key criteria, such as whether the contribution is a measured microarchitectural cost, a buildable mechanism, or a measurable characterization, and how to strategically route the project based on its novelty and evidence.

A comprehensive guide for researchers determining if their cross-layer systems work belongs at ASPLOS or a specialized venue (e.g., ISCA, SOSP, PLDI). It introduces the crucial "deletion test," a routing table based on core claims (microarchitecture, language design, etc.), and criteria for identifying genuine cross-disciplinary intersections between OS, PL, and Architecture.

A comprehensive strategic guide for authors targeting top-tier microarchitecture conferences like MICRO. It covers core topics, required evidence (baselines, workloads, mechanisms), structural expectations, and common pitfalls, ensuring submissions are framed correctly for highly technical audiences.

This guide details the process of preparing complex research artifacts (simulators, configurations, traces, and scripts) for post-acceptance evaluation, especially for microarchitecture papers. It outlines best practices for achieving ACM badges like 'Available' and 'Reproducible,' focusing on structuring the code base with tiered entry points (smoke, key, full) and handling dependencies, licensed data, and simulation time constraints.

A detailed guide on how to write a rigorous and comparative 'Related Work' section for top-tier microarchitecture conferences (e.g., MICRO). It teaches authors to structure the section as a 'mechanism taxonomy,' differentiating designs based on structural and cost differences rather than merely listing citations. Key areas covered include sweeping academic venues, integrating industry disclosures, and verifying all venue attributions using tools like dblp.

A comprehensive guide for microarchitecture researchers on achieving rigorous scientific reproducibility. It mandates tracking every critical artifact—including simulator commits, workload traces, power/area models, and RTL toolchains—and compiling them into a single run manifest, ensuring any reported result can be verified by a third party.

A comprehensive model detailing the entire academic review pipeline for microarchitecture papers, anchored to major conferences like MICRO. It outlines the timeline, from initial submission and double-blind review through the rebuttal/revision window, to final notification. The guide details what expert reviewers focus on—including mechanism novelty, methodology credibility, and cost honesty—providing authors with actionable strategies for strengthening their work through the academic publication lifecycle.

A comprehensive guide designed to help researchers determine the optimal top-tier conference venue for their computer architecture work. It provides detailed criteria—such as mechanism-residency tests, hardware cost analysis, and scope boundaries—to guide authors in correctly placing their research between venues like MICRO, ISCA, ASPLOS, and DAC.

A comprehensive guide for drafting and revising high-level microarchitecture papers for top-tier conferences. It mandates the rigorous 'four-beat argument' structure: starting with characterization evidence, defining the insight, detailing the mechanism, and completing with thorough cost accounting. This ensures the paper is a defensible engineering argument.

This guide helps researchers determine the correct academic venue for their work in parallel and concurrent computing. It clarifies the scope of PPoPP versus related conferences (CGO, PLDI, ASPLOS, HPCA, POPL, etc.) by asking: 'Is the parallelism the point, or is it the setting?' Use this framework to distinguish contributions focused on parallel algorithms, compiler optimization, concurrency theory, or hardware microarchitecture.